An embodiment of the present invention relates to an exposure method and an electronic device manufacturing method. More particularly, the embodiment of the present invention relates to an exposure method used in a lithography process for manufacturing electronic devices such as semiconductor devices, imaging devices, liquid crystal display devices, and thin-film magnetic heads.
A plurality of layers of circuit patterns are formed on a wafer (or a substrate such as a glass plate), which is coated with a photosensitive material, in processes for manufacturing electronic devices such as semiconductor devices. An exposure apparatus is required to align a mask, on which a transferred pattern is formed, and the wafer, on which a circuit pattern has been formed. The exposure apparatus includes an alignment unit for such alignment, which may be, for example, an imaging type alignment unit.
The imaging-device-based alignment unit illuminates a position detection mark (wafer alignment mark) formed on the wafer with light having a wide wavelength band and emitted from a light source such as a halogen lamp. The alignment unit then forms a magnified image of the wafer alignment mark on an imaging device with an imaging optical system and performs image processing on an obtained imaging signal to detect the position of the wafer mark.
A plurality of unit exposure fields are defined on a single wafer in a manner that the unit exposure fields are arranged in a matrix. A circuit pattern or the like corresponding to a functional element, such as a large-scale integrated (LSI) circuit, is formed in each unit exposure field through a single exposure operation (e.g., a one-shot exposure operation or a scanning exposure operation). More specifically, the exposure apparatus repeatedly performs an exposure operation for a single unit exposure field a number of times while step-moving the wafer with respect to a projection optical system. As a result, one or more alignment marks are transferred into each unit exposure field together with one or more LSI circuit patterns.
A conventional position detection apparatus includes a single position detection mechanism (e.g., an alignment microscope) or an X position detection mechanism and a Y position detection mechanism. The wafer on which patterns have been exposed may be deformed in an in-plane direction during wafer processing, which includes etching and film formation. More specifically, the wafer may expand or contract entirely or locally from its original shape due to the wafer processing or the like.
To cope with such deformation of a wafer onto which patterns have been exposed, enhanced global alignment (EGA) has been proposed to correct in-plane deformation of the wafer associated with the arrangement of unit exposure fields. To cope with linear deformation of each unit exposure field, or more specifically, expansion, contraction, and rotation of each unit exposure field, which is expressed by a linear function using orthogonal coordinates representing an in-plane position of each unit exposure field or X and Y coordinates, a magnification correction method for correcting the magnification of the projection optical system and a mask rotation method for rotating the mask have been proposed.
In conventional art, special marks that differ from circuit patterns have been used as position detection marks (also referred to as wafer alignment marks) for alignment purposes. To form the special marks on the wafer, the special marks are transferred onto the unit exposure fields together with circuit patterns. Wafer alignment marks are also formed in a peripheral portion of each unit exposure field (an inner portion extending along a contour boundary of each unit exposure field) so that the LSI design freedom is virtually unaffected by the alignment marks. In addition to the peripheral portion of a unit exposure field or instead of a peripheral portion of a unit exposure field, alignment marks may be formed in a single unit exposure field between two adjacent LSI circuit patterns in a region referred to as a street line when a plurality of LSI circuit patterns are formed in a single unit exposure field.